TDA9106A View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9106A' PDF : 30 Pages View PDF
TDA9106A
OPERATING DESCRIPTION (continued)
Figure 9 : PLL1 Block Diagram
H-LOCKCAP
13
S/G 1
VSYNCIN 33
H/HVIN 38
SYNC
PROCESSOR
TRAMEXT
LOCKDET
COMP1
E2
High
Low
* SMFE : Safety Frequency Mode Enable
Figure 10 : Details of VCO
PLL1INHIB PLL1F R0 C0
LOCK/UNLOCK
3
12 11 10
STATUS
TRAMEXT SMFE *
CHARGE
PUMP
PLL
INHIBITION
H-POS
14
PHASE
ADJUST
VCO
OSC
I2C
HPOS
Adj.
Loop
Filter
12
(1.3V < V12 < 6V)
I0
2
I0
4 I0
11
R0
6.4V
1.6V
RS
FLIP FLOP
9
47nF
8
10 6.4V
C0
1.6V
0 0.875T T
47nF
The control voltage of the VCO is typically com-
prised between 1.33V and 6V (see Figure 10). The
theorical frequency range of this VCO is in the ratio
1 to 4.5, the effective frequency range has to be
smaller 1 to 4.2 due to clamp intervention on filter
lowest value.
The synchro frequency has to be always higher
than the free running frequency. As an example for
a synchro range from 24kHz to 100kHz, the sug-
gested free running frequency is 23kHz.
An other feature is the capability for MCU to force
horizontal frequency through I2C to 2xF0 or 3xF0
(for burn in mode or safety requirement).In this
case, inhibition switch is opened leaving PLL1 free
but voltage on PLL1 filter is forced to 2.66Vfor 2xF0
or 4.0V for 3xF0.
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage
I2C adjustable between 2.8V and 4.0V (corre-
sponding to ± 10%) (see Figure 11). This voltage
has to be filtered on Pin 14 so as to optimize jitter.
The TDA9106A also includes a Lock/Unlock iden-
tification block which senses in real time wheither
PLL1 is locked on the incoming horizontal sync
signal or not. The resulting information is available
on Hlockout (see Synchro Processor). The block
Figure 11 : PLL1 Timing Diagram
H Osc
Sawtooth 7/8TH
1/8TH
Phase REF1
6.4V
2.8V<Vb<4.0V
Vb
1.6V
H Synchro
Phase REF1 is obtained by comparison between the sawtooth and
a DC voltage adjustable between 2.8V and 4.0V. The PLL1 en-
sures the exact coincidence between the signals phase REF and
HSYNS. A ± T/10 phase adjustment is possible.
20/30
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