TDA9109A View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

TDA9109A

LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR

STMicroelectronics 

Prev 11 12 13 14 15 16 17 18 19 20 Next

TDA9109A

Symbol

Parameter

Test Conditions

Min. Typ. Max. Units

2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION

FBt h

Hjit

Flyback Input Threshold Voltage (Pin

12)

Horizontal Jitter (See 7)

At 31.4kHz

0.65 0.75

V

70

ppm

HDmin

HDmax

Horizontal Drive Output Duty-Cycle

(Pin 26) (see 8)

Sub-Address 00

Byte x1111111

Byte x0000000 (see 9)

30

65

%

%

XRAYth

X-RAY Protection Input Threshold

Voltage,

Pin 25, see Figure 14 7.6

8.2

8.8

V

Vphi2

Internal Clamping Levels on 2nd PLL

Loop Filter (Pin 4)

Low Level

High Level

1.6

V

4.2

V

VSCinh

Threshold Voltage to Stop H-Out, V-

Out, B-Out and Reset XRAY when VCC

< VSCinh (see Figure14)

Pin 29

7.5

V

HDvd

Horizontal Drive Output (low level)

Pin 26, IOUT = 30mA

0.4

V

Note: 3

Note: 4

Note: 5

Note: 6

This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync.

See Figure 10 for explanation of reference phase.

These parameters are not tested on each unit. They are measured during our internal qualification.

A larger range may be obtained by application.

Note: 7

Note: 8

Note: 9

Hjit = 106 x (Standard deviation/Horizontal period)

Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is

controlled OFF when the output transistor is OFF.

Initial Condition for Safe Operation Start Up.

12/47

Share Link: