TDA9109SN View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9109SN' PDF : 30 Pages View PDF
TDA9109/SN
OPERATING DESCRIPTION (continued)
I.6 - Sync Identification Status
The MCU can read (address read mode : 8D) the
status register via the I2C bus, and then select the
sync priority depending on this status.
Among other data this register indicates the pres-
ence of sync pulses on H/HVIN, VSYNCIN and
(when 12V is supplied) whether a Vext has been
extracted from H/HVIN. Both horizontaland vertical
sync are detected even if only 5V is supplied.
In order to choose the right sync priority the MCU
may proceed as follows (see I2C Address Table) :
- refresh the status register,
- wait at least for 20ms (Max. vertical period),
- read this status register.
Sync priority choice should be :
Vext H/V
det det
V
det
Sync priority
Subaddress
03 (D8)
Comment
Sync type
No Yes Yes
1
Separated H & V
Yes Yes No
0
Composite TTL H&V
Ofcourse, when the choice is made, we can refresh
the sync detections and verify that the extracted
Vsync is present and that no sync type change has
occured. The sync processor also gives sync po-
larity information.
I.7 - IC status
The IC can inform the MCU about the 1st horizontal
PLL and vertical section status (locked or not) and
about the XRAY protection (activated or not).
Resetting the XRAY internal latch can be done
either by decreasing the VCC or VDD supply or
directly resetting it via the I2C interface.
I.8 - Sync Inputs
Both H/HVIN and VSYNCIN inputs are TTL com-
patible triggers with hysterisis to avoid erratic
detection. Both inputs include a pull up resistor
connected to VDD.
I.9 - Sync Processor Output
The sync processor indicates on the HLOCKOUT
Pin whether 1st PLL is locked to an incoming
horizontal sync. HLOCKOUT is a TTL compatible
CMOS output. Its level goes to high when locked.
In the same time the D8 bit of the status register is
set to 0.
This information is mainly used to trigger safety
procedures (like reducing B+ value) as soon as a
change is detected on the incoming sync.
II - HORIZONTAL PART
II.1 - Internal Input Conditions
A digital signal (horizontal sync pulse or TTL
composite) is sent by the sync processor to the
horizontal input. It may be positiveornegative (see
Figure 5).
Figure 5
Using internal integration, both signals are recog-
nized if Z/T < 25%. Synchronization occurs on the
leading edge of the internal sync signal. The mini-
mum value of Z is 0.7µs.
Another integration is able to extract the vertical
pulse from compositesync if the duty cycle is higher
than 25% (typically d = 35%) (see Figure 6).
Figure 6
C
d
d
TRAMEXT
The last feature performed is the removal of equali-
zation pulses to avoid parasitic pulses on the phase
comparator (which would be disturbed by missing
or extraneous pulses).
II.2 - PLL1
The PLL1 consists of a phase comparator, an
external filter and a voltage-controlled oscilla-
tor (VCO).
The phase comparator is a ”phase frequency”type
designed in CMOS technology. This kind of phase
detector avoids locking on wrong frequencies. It is
followed by a ”charge pump”, composed of two
current sources : sunk and sourced (typi-
cally I = 1mA when locked and I = 140µA when
unlocked). This difference between lock/unlock al-
lows smooth catching of the horizontal frequency
by PLL1. This effect is reinforced by an internal
original slow down system when PLL1 is locked,
avoiding the horizontal frequency changing too
quickly.
The dynamic behaviour of PLL1 is fixed by an
external filter which integrates the current of the
charge pump. A ”CRC” filter is generally used
(see Figure 7).
17/30
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