TDA9113 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9113' PDF : 50 Pages View PDF
TDA9113
Sad17/D2 - HBOutEn
Horizontal and B+ Output Enable
0: Disabled, levels corresponding to “power
transistor off” on HOut and BOut pins (high
for HOut, high or low for BOut, depending
on BOutPol bit).
1: Enabled, horizontal deflection drive signal
on HOut pin providing that it is not inhibited
by another internal event (activated XRay
protection). B+ drive signal on BOut pin.
Programming the bit to 1 after prior value of 0,
will initiate soft start mechanism of horizontal
drive and of B+ DC/DC convertor if this is in ex-
ternal sawtooth configuration.
SadXX/D2 - VExtrDet (52)
Flag indicating Detection of Extracted Vertical
synchronization signal from composite H+V sig-
nal applied on H/HVSyn pin
0: Not detected
1: Detected
SadXX/D3 - VPol
Flag indicating Polarity of V synchronization
pulses applied on VSyn pin with respect to mean
level of the sync signal
0: Positive
1: Negative
Sad17/D3 - BOHEdge
Selection of Edge of Horizontal drive signal to
phase B+ drive Output signal on BOut pin. Only
applies if the bit BOutPh is set to 1, otherwise
BOHEdge has no effect.
0: Falling edge
1: Rising edge
SadXX/D4 - HVPol
Flag indicating Polarity of H or HV synchroniza-
tion pulses applied on H/HVSyn pin with respect
to mean level of the sync signal
0: Positive
1: Negative
SadXX/D5 - XRayAlarm
Sad17/D4,D5,D6,D7 - THM, TVM, TH, TV
Test bits. They must be kept at 0 level by appli-
cation S/W.
Alarm indicating that an event of excessive volt-
age has passed on XRay pin. Can only be reset
to 0 through I2C Bus bit XRayReset or by power-
on reset.
Read-out flags
SadXX/D0 - VDet(52)
0: No excess since last reset of the bit
1: At least one event of excess appeared
since the last reset of the bit, HOut inhibited
Flag indicating Detection of V synchronization
pulses on VSyn pin.
0: Not detected
1: Detected
SadXX/D6 - VLock
Status of “Locking” or stabilization of Vertical os-
cillator amplitude to an internal reference by
AGC regulation loop.
SadXX/D1 - HVDet (52)
Flag indicating Detection of H or HV synchroni-
zation pulses applied on H/HVSyn pin. Once the
sync pulses are detected, the flag is set and
latched. Disappearance of the sync signal will
not lead to reset of the flag.
0: Not detected
1: Detected.
0: Locked (amplitude stabilized)
1: Not locked (amplitude non-stabilized)
SadXX/D7 - HLock
Status of Locking of Horizontal PLL1
0: Locked
1: Not locked
Note 52: This flag, by its value of 1, indicates an event of detection of at least one synchronization pulse since its last
reset (by means of the SDetReset I2C Bus bit). This is to be taken into account by application S/W in a way that
enough time (at least the period between 2 synchronization pulses of analyzed signal) must be provided
between reset of the flag through SDetReset bit and validation of information provided in the flag after read-out
of status register.
25/50
Share Link: 
