TDA9113 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9113' PDF : 50 Pages View PDF
TDA9113
band even while locked. The speed of the PLL1
depends on the current value provided by the
charge pump. While not locked, the current is very
low, to slow down the changes of VCO frequency
and thus protect the external power components
at sync. signal change. In locked state, the cur-
rents are much higher, two different values being
selectable via PLL1Pump I2C bus bit to provide a
mean to control the PLL1 speed by S/W. Lower
values make the PLL1 slower, but more stable.
Higher values make it faster and less stable. In
general, the PLL1 speed should be higher for high
deflection frequencies. The response speed and
stability (jitter level) depends on the choice of ex-
ternal components making up the loop filter. A
“CRC” filter is generally used (see Figure 4 on
page 28).
Figure 5. Horizontal PLL1 block diagram
H/HVSyn
1
Sync
Polarity
INPUT
INTERFACE
Extracted
V-sync
00000000000000000000000000000000
PLL1
LOCK
DETECTOR
High
COMP
Low
REF1
Figure 4. H-PLL1 filter configuration
HPLL1F
9
R2
C1
C2
The PLL1 is internally inhibited during extracted
vertical sync. pulse (if any) to avoid taking into ac-
count missing or wrong pulses on the phase com-
parator. Inhibition is obtained by forcing the charge
pump output to high impedance state. The inhibi-
tion mechanism can be disabled through
PLL1Pump I2C bus bit.
The Figure 7, in its upper part, shows the position
of the VCO ramp signal in relation to input sync.
pulse for three different positions of adjustment of
horizontal position control HPOS.
PLL1InhEn
(I2C) V-sync (extracted)
Lock
Status
(pin & I2C)
HPLL1F R0
98
C0 HOscF
64
CHARGE
PUMP
PLL1Pump
(I2C)
PLL
INHIBITION
HPosF
10
SHAPER
VCO
HOSC
HPOS
(I2C)
28/50
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