TDA9115 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9115' PDF : 45 Pages View PDF
TDA9115
Figure 4. H-PLL1 filter configuration
HPLL1F
9
R2
C1
C2
pump output to high impedance state. The inhibi-
tion mechanism can be disabled through
PLL1Pump I2C bus bit.
The Figure 7, in its upper part, shows the position
of the VCO ramp signal in relation to input sync.
pulse for three different positions of adjustment of
horizontal position control HPOS.
The PLL1 is internally inhibited during extracted
vertical sync. pulse (if any) to avoid taking into ac-
count missing or wrong pulses on the phase com-
parator. Inhibition is obtained by forcing the charge
Figure 5. Horizontal PLL1 block diagram
H/HVSyn
1
Sync
Polarity
INPUT
INTERFACE
Extracted
V-sync
PLL1
LOCK
DETECTOR
High
COMP
Low
REF1
PLL1InhEn
(I2C) V-sync (extracted)
Lock
Status
(pin & I2C)
HPLL1F R0
98
C0 HOscF
64
CHARGE
PUMP
PLL1Pump
(I2C)
PLL
INHIBITION
HPosF
10
SHAPER
VCO
HOSC
HPOS
(I2C)
Figure 6. Horizontal oscillator (VCO) schematic diagram
(PLL1 filter)
HPLL1F 9 VHO +
-
from charge pump
I0
I0
2
4 I0
RO 8
4
VHOThrHi
HOscF
+
-
-
VHOThrLo +
RS
Flip-Flop
6 CO
VHOThrHi
VHOThrLo
VCO discharge
control
25/45
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