TDA9115 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TDA9115' PDF : 45 Pages View PDF
TDA9115
Figure 7. Horizontal timing diagram
H-sync
(polarized)
tHph
min max
PLL1 lock
REF 1
(internal)
H-Osc
(VCO )
VHPosF
max.
med.
min.
VS(0)
7/8TH
TH
HPOS
(I2C)
max.
med.
min.
VHOThrHi
VHOThrLo
H-flyback
VThrHFly
PLL2
control
current
H-drive
(on HOut)
H-drive
region
H-drive
region
tS +
-
ON
ON
OFF
tHoff
forced high forced low
tph(max)
inhibited
tS: HOT storage time
Figure 8. HFly input configuration
HFly 12
~500Ω
~20kΩ
ext. int.
GND
9.3.6 Output section
The H-drive signal is inhibited (high level) during
flyback pulse, and also
I2C bus bit HBOutEn is
when
set to
VCC is too
0 (default
low, when
position).
The PLL2 is followed by a rapid phase shifting
which accepts the signal from H-moiré canceller
(see sub chapter Horizontal moiré cancellation on
page 27)
The output stage consists of a NPN bipolar tran-
sistor, the collector of which is routed to HOut pin
(see Figure 9).
Figure 9. HOut configuration
26 HOut
int. ext.
Non-conductive state of HOT (Horizontal Output
Transistor) must correspond to non-conductive
state of the device output transistor.
9.3.7 Soft-start and soft-stop on H-drive
The soft-start and soft-stop procedure is carried
out at each switch-on or switch-off of the H-drive
signal via HBOutEn I2C bus bit to protect external
power components. By its second function, the ex-
ternal capacitor on pin HPosF is used to time out
this procedure, during which the duty cycle of H-
drive signal starts at its maximum (“tHoff/TH for soft
start/stop” in electrical specifications) and slowly
decreases. This is controlled by voltage on pin
HPosF. See Figure 10 and sub chapter Safety
functions on page 33.
9.3.8 Horizontal moiré cancellation
The horizontal moiré canceller is intended to blur a
potential beat between the horizontal video pixel
period and the CRT pixel width, which causes vis-
ible moiré patterns in the picture.
On pin HMoiré, it generates a square line-synchro-
nized waveform with amplitude adjustable through
HMOIRE I2C bus control.
The behaviour of horizontal moiré is to be opti-
mised for different deflection design configurations
using HMoiré I2C bus bit. This bit is to be kept at 0
for common architecture (B+ and EHT common
regulation) and at 1 for separated architecture (B+
and EHT each regulated separately).
27/45
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