TS68HC901 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TS68HC901' PDF : 42 Pages View PDF
TS68HC901
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5.0Vdc ± 5%, GND = 0Vdc, TA = 0°C to 70°C)
Number
30(6)
31(2)
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49(2)
50
Characteristic
Timer Output Low from Rising Edge of
CS or DS (A & B) (reset TOUT)
TOUT Valid from Internal Timeout
Timer Clock Low Time
Timer Clock High Time
Timer Clock Cycle Time
RESET Low Time
Delay to Falling INTR from External
Interrupt Active Transition
Transmitter Internal Interrupt Delay
from Falling Edge of TC
Receiver Buffer Full Interrupt
Transition Delay from Rising Edge of
RC
Receiver Error Interrupt Transition
Delay from Falling Edge of RC
Serial in Set Up Time to Rising Edge
of RC (divide by one only)
Data Hold Time from Rising Edge of
RC
(divide by one only)
Serial Output Data Valid from Falling
Edge of TC (÷1)
Transmitter Clock Low Time
Transmitter Clock High Time
Transmitter Clock Cycle Time
Receiver Clock Low Time
Receiver Clock High Time
Receiver Clock Cycle Time
CS, IACK, DS Width Low
Serial Output Data Valid from Falling
Edge of TC (÷16)
4MHz
Min. Max.
450
2 tCLK
+ 300
110
110
250 1000
2
380
550
800
800
80
350
440
500
500
1.05
500
500
1.05
80
490
Value
5MHz
Min. Max.
450
2 tCLK
+ 300
90
90
200 1000
1.8
380
550
800
800
70
325
420
450
450
0.95
450
450
0.95
80
370
8MHz
Min. Max.
200
2 tCLK
+ 300
55
55
125 1000
1.5
250
350
400
400
50
100
200
250
250
0.55
250
250
0.55
80
250
Unit
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
TCLK
ns
Notes :
2. TCLK refers to the clock applied to the MFP CLK input
pin. tCLK refers to the timer clock signal, regardless of
whetherthat signal comes from theXTAL 1/XTAL2 crys-
tal clock inputs or the TAI or TBI timer inputs.
6. Spec. 30 applies to timer outputs TAO and TBO only.
31/42
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