TS68HC901 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TS68HC901' PDF : 42 Pages View PDF
TS68HC901
Figure 14 :
7
TIMER A CONTROL REGISTER
0
TACR
(19h)
0*
0*
0*
TA0
RESET
AC3
AC2
AC1
AC0
TIMER B CONTROL REGISTER
TBCR
0*
(1Bh)
0*
0*
TB0
RESET
BC3
BC2
BC1
BC0
CLEARED on RESET
0*
Unused bits, read as zero.
RESET Timer’s A and B output lines (TA0 and TB0) may be forced low at any time by writing a one
TA0/TB0 to the reset location in TACR and TBCR, respectively. The output will be held low only during
the write operation ; at the conclusion of the operation the output will be allowed to toggle in
response to a time-out pulse. When resetting TA0 and TB0, the remaining bits in the control
register must be written with their previous value to avoid altering the operation mode.
SET: End of write cycle which clears the bit
CLEARED: MPUwrites a zero
AC3-AC0 These bits are decoded to determine the timer operation mode.
BC3-BC0
AC3
BC3
AC2
BC2
AC1
BC1
AC0
BC0
Operation Mode
0
0
0
0
Timer Stopped*
0
0
0
1
Delay Mode, ÷ 4 Prescaler
0
0
1
0
Delay Mode, ÷ 10 Prescaler
0
0
1
1
Delay Mode, ÷ 16 Prescaler
0
1
0
0
Delay Mode, ÷ 50 Prescaler
0
1
0
1
Delay Mode, ÷ 64 Prescaler
0
1
1
0
Delay Mode, ÷ 100 Prescaler
0
1
1
1
Delay Mode, ÷ 200 Prescaler
1
0
0
0
Event Count Mode
1
0
0
1
Pulse Width Mode, ÷ 4 Prescaler
1
0
1
0
Pulse Width Mode, ÷ 10 Prescaler
1
0
1
1
Pulse Width Mode, ÷ 16 Prescaler
1
1
0
0
Pulse Width Mode, ÷ 50 Prescaler
1
1
0
1
Pulse Width Mode, ÷ 64 Prescaler
1
1
1
0
Pulse Width Mode, ÷ 100 Prescaler
1
1
1
1
Pulse Width Mode, ÷ 200 Prescaler
* Regardless of the operation mode, counting is inhibited when the timer is stopped. The
contents of the timer’s main counter is not affected, although any residual count in the
prescaler is lost.
SET: End of write cycle which clears the bit
CLEARED: MPUwrites a zero
21/42
®
Share Link: 
