TS68HC901 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TS68HC901' PDF : 42 Pages View PDF
TS68HC901
SET : Incoming word received and receive buffer full
CLEARED : Receiver status register read
Receiver Status Register (Continued)
PE
Parity Error. This bit is set when the word transferred to the receive buffer has a parity error.
This bit is cleared when the word transferred to the receive buffer does not have a parity error.
SET : Word in receive buffer has a parity error
CLEARED : Word in receive buffer does not have a parity error
FE
Frame Error. A frame error exists when a non-zero data word is not followed by a stop bit in
the asynchronous character format. The FE bit is set when the word transferred to the receive
buffer has a frame error. The FE bit is cleared when the word transferred to the receive buffer
does not have a frame error.
SET : Word in receive buffer has a frame error
CLEARED : Word in receive buffer does not have a frame error
F/S or B Found/Search or Break Detect. In the synchronous character format this bit can be set or clea-
red by software. When the bit is a zero, the USART receiver is placed in the search mode.
The incoming data is compared to the synchronous character register (SCR) and the word
length counter is disabled. The F/S bit will automatically be set when a match is found and
the word length counter will be enabled. An interrupt will also be produced on the receive error
channel.
SET : Incoming word matches synchronous character
CLEARED : MPU writes a zero or Incoming word does not match synchronous character
In the asynchronous character format, this flag indicates a break condition. A break is detec-
ted when an all zero data word with no stop bit is received. The break condition continues
until a non-zero data bit is received. The 8-bit is set when the word transferred to the receive
buffer is a break indication. A break condition generates an interrupt to the processor. This
bit is cleared when a non-zero data bit is received and the break condition has been acknow-
ledged by reading the RSR at least once. An end of break interrupt will be generated when
the bit is cleared.
SET : Word in receive buffer is a break
CLEARED : Break terminates and receiver status register read since beginning of break condition
M or CIP Match/Character in Progress. In the synchronous format, this flag indicates that a synchro-
nous character has been received. The M bit is set when the word transferred to the receive
buffer matches the synchronous character register. The M bit is cleared when the word trans-
ferred to the receive buffer does not match the synchronous character register.
SET : Word transferred to receive buffer matches the synchronous character
CLEARED : Word transferred to receive buffer does not match synchronous character
In the asynchronous character format, this flag indicates that a word is being assembled. The
CIP bit is set when a start bit is detected. The CIP bit is cleared when the final stop bit has
been received.
SET : Start bit is detected
CLEARED : End of word detected
SS
Synchronous Strip Enable. When this bit is a one, data words that match the synchronous
character register will not be loaded into the receive buffer and no buffer full condition will be
produced. When this bit is a zero, data words that match the synchronous character register
will be transferred to the receive buffer and a buffer full condition will be produced.
SET : MPU writes a one
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