TS68HC901 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TS68HC901' PDF : 42 Pages View PDF
TS68HC901
Figure 15 :
7
TCDCR
(1Dh)
0*
TIMER C AND D CONTROL REGISTER
0
CC2
CC1
CC0
0*
CLEARED on RESET
DC2
DC1
DC0
0*
Unused bits, read as zero.
CC2-CC0 These bits are decoded to determine the timer operation mode.
DC2-DC0
CC2
DC2
CC1
DC1
CC0
DC0
Operation Mode
0
0
0
Timer Stopped*
0
0
1
Delay Mode, ÷ 4 Prescaler
0
1
0
Delay Mode, ÷ 10 Prescaler
0
1
1
Delay Mode, ÷ 16 Prescaler
1
0
0
Delay Mode, ÷ 50 Prescaler
1
0
1
Delay Mode, ÷ 64 Prescaler
1
1
0
Delay Mode, ÷ 100 Prescaler
1
1
1
Delay Mode, ÷ 200 Prescaler
* Regardless of the operation mode, counting is inhibited when the timer is stopped.
The contents of the timer’s main counter is not affected, although any residual count in
the prescaler is lost.
SET: End of write cycle which clears the bit
CLEARED: MPUwrites a zero
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