TS68HC901 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TS68HC901' PDF : 42 Pages View PDF
TS68HC901
SYNC
0 0 0 0 ASYN
0
01 1 1 C
0
1 0 1 11/2 ASYN
1
1 1 1 2 C*
1
ASYN
C
0 8 Bits
1 7 Bits
0 6 Bits
1 5 Bits
(*) : Only used with divide-by-16 clock mode
RECEIVER INTERRUPT CHANNELS
The USART receive section is assigned two inter-
rupt channels. One indicates the buffer full condi-
tion, while the other channel indicates an error
condition. Error conditions include overrun, parity
error, synchronous found, and break. These inter-
rupting conditions correspond to the BF, OE, PE,
and F/S or B bits of the receiver status register.
These flags will function as described in 6.2.2. whe-
ther the receiver interrupt channels are enabled or
disabled.
While only one interrupt is generated per character
received, two dedicated interrupt channels allow se-
parate vector numbers to be assigned for normal
and abnormal receiver conditions. When a received
word has an error associated with it and the error in-
terrupt channel is enabled, an interrupt will be gene-
rated on the error channel only. However, if the error
channel is disabled, an interrupt for an error condi-
tion will be generated on the buffer full interrupt
channel along with interrupts produced by the buffer
full condition. The receiver status register must al-
ways be read to determine which error condition
produced the interrupt.
RECEIVER STATUS REGISTER
The receiver status register contains the receive
buffer full flag, the synchronous strip enable, the re-
ceiver enable, and various status information asso-
ciated with the data word in the receive buffer. The
RSR is latched each time a data word is transferred
to the receive buffer. RSR flags cannot change a-
gain until the data word has been read. The exception
is the character in progress flag which monitors when
a new word is being assembled in the asynchronous
character format. The receiver status register is
shown in Figure 18.
SPECIAL RECEIVE CONSIDERATIONS
Figure 18 :
7
RECEIVER STATUS REGISTER
0
RSR
(2Bh)
BF
OE
PE
FE
F/S or B
M/CIP
SS
RE
CLEARED on RESET
Certain receive conditions relating to the overrun error flag and the break defect flag require further ex-
planation. Consider the following examples :
1) A break is received while the receive buffer is full. This does not produce an overrun condition. Only
the B flag will be set after the receiver buffer is read.
2) A new word is received and the receive buffer is full. A break is received before the receive buffer is
read.
Both the B and OE flags will be set when the buffer full condition is satisfied.
BF
Buffer Full. This bit is set when a received word is transferred to the receive buffer. This bit
is cleared when the receive buffer is read by accessing the USART data register (UDR). This
bit is read only.
SET : Received word transferred to buffer
CLEARED : Receive buffer read
OE
Overrun Error. An overrun error occurs when a received word is due to be transferred to the
receive buffer, but the receive buffer is full. Neither the receive buffer nor the RSR is overw-
ritten. The OE bit is set after the receive buffer full condition is satisfied by reading the UDR.
This error condition will generate an interrupt to the processor. The OE bit is cleared by rea-
ding the RSR. New data words will not be assembled until the RSR is read.
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