TS68HC901 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TS68HC901' PDF : 42 Pages View PDF
TS68HC901
CLEARED : MPU writes a zero
RE
Receiver Enable. When this bit is a zero,
the receiver will be immediately disabled.
All flags will be cleared. When this bit is
a one, normal receiver operation is en-
abled. This bit should no be set to a one
until the receiver clock is active.
SET : MPU writes a one or Transmitter is disabled in
auto-turnaround mode
CLEARED : MPU writes a zero
TRANSMITTER
The transmit buffer is loaded by writing to the U-
SART data register (UDR). The data word will be
transferred to an internal 8-bit shift register when the
last word in the shift register has been transmitted.
This will produce a buffer empty condition. If the
transmitter completes the transmission of word in
the shift register before a new word is written to the
transmit buffer, an underrun error will occur. In the
asynchronous character format, the transmitter will
send a mark until the transmit buffer is written. In the
synchronous character format, the transmitter will
continuously send the synchronous character.
The transmit buffer can be loaded prior to enabling
the transmitter. After the transmitter is enabled,
there is a delay before the first bit is output. The se-
rial output line (SO) should be programmed to be
high, low, or high impedance when the transmitter
is enabled to force the output line to the desired state
until the first bit is shifted out. Note that a one bit will
always be transmitted prior to the word in the trans-
mit shift register when the transmitter is first en-
abled.
When the transmitter is disabled, any word currently
being transmitted will continue to completion. How-
ever, any word in the transmit buffer will not be trans-
mitted and will remain in the buffer. So, no buffer
empty condition will occur. If the buffer is empty
when the transmitter is disabled, the buffer empty
condition will remain, but no underrun condition will
be generated when the word in transmission is
completed. If no word is being transmitted when the
transmitter is disabled, the transmitter will stop at the
next rising edge of the internal shift clock.
In the asynchronous character format, the transmit-
ter can be programmed to send a break. The break
will be transmitted once the word currently in the
shift register has been sent. If the shift register is
empty, the break command will be effective imme-
diately. An END interrupt will be generated at every
normal character boundary to aid in timing the break
transmission. The break will continue until the break
command is cleared.
Any character in the transmit buffer at the start of a
break will be transmitted when the break is termina-
ted. If the transmit buffer is empty at the start of a
break, it may be written at any time during the break.
If the buffer is still empty at the end of the break, an
underrun condition will exist.
Disabling the transmitter during a break condition
causes the transmitter to cease transmission of the
break character at the end of the current character.
No end of break stop bit will be transmitted. Even if
the transmit buffer is empty, no buffer empty condi-
tion will occur nor will an underrun condition occur.
Also, any word in the transmit buffer will remain.
TRANSMITTER INTERRUPT CHANNELS
The USART transmit section is assigned two inter-
rrupt channels. One channel indicates a buffer emp-
ty condition and the other channel indicates an un-
derrun or end condition. These interrupting condi-
tions correspond to the BE, UE, and END flag bits
of the transmitter status register (TSR). The flag bits
will function as described below, whether their asso-
ciated interrupt channel is enabled or disabled.
TRANSMITTER STATUS REGISTER
The transmitter status register contains various
transmitter error flags and transmitter control bits for
selecting auto-turnaround and loopback mode. The
TSR is shown in Figure 19.
DMA OPERATION
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