TS68HC901 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'TS68HC901' PDF : 42 Pages View PDF
TS68HC901
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0Vdc ± 5%, GND = 0Vdc, TA = 0°C to 70°C)
Number
1
2
3
4(3)
4a(4)
5
6
7
8
9
10
11(3,5)
12
Characteristic
CS, DS Width High
R/W, A1-A5 Valid to Falling CS (setup)
Data Valid Prior to Falling CLK
CS, IACK Valid to Falling Clock (setup)
Falling Clock to Next CS Low
CLK Low to DTACK Low
CS, DS or IACK High to DTACK High
CS, DS or IACK High to DTACK Tri-state
DTACK Low to Data Invalid (hold time)
CS, DS or IACK High to Data Tri-state
CS or DS High to R/W, A1-A5 Invalid
(hold time)
Data Valid from CS Low
Read Data Valid to DTACK Low (setup)
4MHz
Min. Max.
50
30
280
50
100
220
60
100
0
50
0
310
50
Value
5MHz
Min. Max.
35
25
150
50
80
180
55
100
0
50
0
260
50
8MHz
Min. Max.
25
20
100
50
50
90
50
100
0
50
0
200
20
13
14
15(1)
16
17
18
19(1)
20
DTACK Low to DS, CS or IACK High
(hold time)
IEI Low to Falling CLK (setup)
IEO Valid from Clock Low (delay)
Data Valid from Clock Low (delay)
IEO Invalid from IACK High (delay)
DTACK Low from Clock High (delay)
IEO Valid from IEI Low (delay)
Data Valid from IEI Low (delay)
0
0
0
50
50
50
180
180
120
300
300
180
150
150
100
180
165
100
100
100
100
220
220
195
21
Clock Cycle Time
22
Clock Width Low
250 1000 200 1000 125 1000
110
90
55
23
Clock Width High
110
90
55
24(4) DS Inactive to rising Clock (setup)
100
80
50
25
I/O Minimum Active Pulse Width
100
100
100
26
IACK Width High
2
2
2
27
I/O Data Valid from Rising CS or DS
28
Receiver Ready Delay from Rising RC
450
450
350
600
600
200
29
Transmitter Ready Delay from Rising TC
600
600
200
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCLK
ns
ns
ns
Notes :
1. IEO only goes low if no acknowledgeable interrupt is
pending. If IEO goes low, DTACK and the data bus re-
main tri-stated.
2. TCLK refers to the clock applied to the MFP CLK input
pin. tCLK refers to the timer clock signal, regardless of
whetherthat signal comes from theXTAL 1/XTAL2 crys-
tal clock inputs or the TAI or TBI timer inputs.
3. If the setup time is not met, CS or IACK will not be reco-
gnized until the next falling CLK.
4. If this setup time is met (for consecutive cycles), the mi-
nimum hold-off time of one clock cycle will be obtained.
If not met, the hold-off will be two clock cycles.
5. Although CS and DTACK are synchronized with the
clock, the data out during a read cycle is asynchronous
to the clock, relying only on CS for timing.
6. Spec. 30 applies to timer outputs TAO and TBO only.
30/42
®
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