UPD78P058F View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
MFG CO.
'UPD78P058F' PDF : 415 Pages View PDF
CHAPTER 1 GENERAL
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
TO1/P31
TI1/P33
TO2/P32
TI2/P34
Figure 1-4. Block Diagram of µPD78064Y Subseries
16-bit TIMER/
EVENT COUNTER
8-bit TIMER/EVENT
COUNTER 1
8-bit TIMER/EVENT
COUNTER 2
PORT0
PORT1
PORT2
PORT3
WATCHDOG TIMER
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SDL/P27
WATCH TIMER
SERIAL
INTERFACE 0
78K/0
CPU CORE
ROM
PORT7
PORT8
PORT9
PORT10
SI2/RXD/P70
SO2/TXD/P71
SCK2/ASCK/P72
ANI0/P10-
ANI7/P17
AVDD
AVSS
AVREF
SERIAL
INTERFACE 2
A/D CONVERTER
INTP0/P00-
INTP5/P05
INTERRUPT
CONTROL
RAM
PORT11
LCD
CONTROLLER/
DRIVER
BUZ/P36
BUZZER OUTPUT
PCL/P35
CLOCK OUTPUT
CONTROL
VDD VSS IC
SYSTEM
CONTROL
P00
P01-P05
P07
P10-P17
P25-P27
P30-P37
P70-P72
P80-P87
P90-P97
P100-P103
P110-P117
S0-S23
S24/P97-
S31/P90
S32/P87-
S39/P80
COM0-COM3
VLC0-VLC2
BIAS
fLCD
RESET
X1
X2
XT1/P07
XT2
Remark The internal ROM and RAM capacities differ depending on the model.
12
Share Link: 
