UPD78P058F View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
MFG CO.
'UPD78P058F' PDF : 415 Pages View PDF
CHAPTER 1 GENERAL
Table 1-10. Functional Outline of µPD780018Y Subseries (1/2)
Part Number
Item
µPD780016Y
µPD780018Y
µPD78P018Y
Internal ROM
memory
Mask ROM
48K bytes
60K bytes
PROM
60K bytesNote
High-speed RAM 1024 bytes
Buffer RAM
32 bytes
Expansion RAM 1024 bytes
Memory space
64K bytes
General-purpose register 8 bits × 8 × 4 banks
Minimum With main
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 5.0 MHz)
instruction system clock
execution With subsystem 122 µs (at 32.768 kHz)
time
clock
Instruction set
• 16-bit operation
• Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjustment, etc.
I/O port
• Total
• CMOS input
• CMOS I/O
: 88
:9
: 79
A/D converter
8-bit resolution × 8 channels
Serial interface
• 3-wire serial I/O mode (with automatical transfer/reception function)
• 3-wire serial I/O mode selectable (with time-division transfer function)
• I2C bus mode (multi-master compatible)
: 1 channel
: 1 channel
: 1 channel
Timer
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 4 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
Timer output
5 (14-bit PWM output: 1, 8-bit PWM output: 2)
Clock output
39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main
system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)
Note The internal PROM capacity can be changed by using a memory size select register. (IMS)
Caution The µPD780018Y subseries is under development.
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