UPD78P4916GF-3BA View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
MFG CO.
'UPD78P4916GF-3BA' PDF : 56 Pages View PDF
µPD78P4916
AC Characteristics
CPU and peripheral unit operation clocks (TA = –10 to +70 ˚C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
TYP. Unit
CPU operation clock cycle time
tCLK
fXX = 16 MHz VDD = AVDD = 4.0 to 5.5 V
CPU function only
125
ns
fXX = 16 MHz
fXX = 8 MHz, Low frequency oscillation mode (CC bit7 = 1)
Peripheral unit operation clock
cycle time
tCLK1
fXX = 16 MHz
125
ns
fXX = 8 MHz, Low frequency oscillation mode (CC bit7 = 1)
Serial interface
(1) SIOn: n = 1, 2 (TA = –10 to +70 ˚C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Serial clock cycle time
Serial clock high/low level width
SIn set-up time (to SCKn ↑)
SIn hold time (from SCKn ↑)
SOn output delay time (from SCKn ↓)
Symbol
tCYSK
tWSKH
tWSKL
tSSSK
tHSSK
tDSSK
Input
Output
Input
Output
Conditions
External clock
fCLK1/8
fCLK1/16
fCLK1/32
fCLK1/64
fCLK1/128
fCLK1/256
External clock
Internal clock
MIN. MAX. Unit
1.0
µs
1.0
µs
2.0
µs
4.0
µs
8.0
µs
16
µs
32
µs
420
ns
tCYSK/2–50
ns
100
ns
400
ns
0
300
ns
Remarks 1. fCLK1: Operation clock for peripheral unit (8 MHz)
2. n = 1, 2
(2) Only SIO2 (TA= –10 to +70 ˚C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
SCK2(8) ↑ → STRB ↑
Strobe high level width
BUSY setup time (to BUSY detection timing)
BUSY hold time (from BUSY detection timing)
Busy inactive → SCK2(1) ↓
Symbol
tDSTRB
tWSTRB
tSBUSY
tHBUSY
tLBUSY
Conditions
MIN. MAX.
tWSKH
tCYSK
tCYSK–30 tCYSK+30
100
100
tCYSK+tWSKH
Unit
ns
ns
ns
Remarks 1. The value in the parentheses following SCK2 indicates the sequential number of the SCK2.
2. BUSY detection timing is (n + 2) × tCYSK (n = 0, 1,...) after SCK2(8) ↑.
3. BUSY inactive → SCK2(1) ↓ is a value at the time data is already written in SIO2.
31
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