V826632G24S View Datasheet(PDF) - Mosel Vitelic Corporation
Part Name
Description
MFG CO.
'V826632G24S' PDF : 14 Pages View PDF
MOSEL VITELIC
V826632G24S
DDR SDRAM IDD SPEC TABLE
Symbol
C0(DDR333@CL=2.5) B1(DDR266@CL=2) B0(DDR266@CL=2.5) A1(DDR200@CL=2)
Unit
Typical
Typical
Typical
Typical
IDD0
880
800
800
640
mA
IDD1
1120
1000
1000
800
mA
IDD2P
200
200
200
160
mA
IDD2F
365
360
360
320
mA
IDD2Q
340
280
280
240
mA
IDD3P
240
240
240
200
mA
IDD3N
460
400
400
320
mA
IDD4R
1360
1360
1360
1120
mA
IDD4W
1680
1480
1480
1200
mA
IDD5
1600
1480
1480
1200
mA
IDD6 Normal
24
24
24
24
mA
Low power
15
15
15
15
mA
IDD7A
2800
2600
2600
2120
mA
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
V826632G24S Rev. 1.1 July 2002
9
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