VG26V18165C View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG26V18165C' PDF : 27 Pages View PDF
VIS
VG26(V)(S)18165C/VG26(V)(S)18165D
1,048,576 x 16 - Bit
CMOS Dynamic RAM
Refresh Cycle
Parameter
Symbol
LCAS / UCAS setup time (CBR refresh)
LCAS / UCAS hold time (CBR refresh)
RAS precharge to CAS hold time
RAS pulse width (self refresh)
RAS precharge time (self refresh)
LCAS / UCAS hold time (CBR self refresh)
WE setup time
WE hold time
tCSR
tCHR
tRPC
tRASS
tRPS
tCHS
tWSR
tWHR
VG26(V)(S)18165
-5
-6
Min
Max
Min
Max Unit
5
-
5
- ns
8
-
10
- ns
5
-
5
- ns
100
-
100
- µs
90
-
110
- ns
-50
-
-50
- ns
0
-
0
- ns
10
-
10
- ns
Notes
11
8
EDO Page Mode Cycle
Parameter
Symbol
EDO page mode cycle time
EDO page mode LCAS / UCAS precharge
time
EDO page mode RAS pulse width
Access time from LCAS / UCAS precharge
RAS hold time from LCAS / UCAS pre-
charge
OE high hold time from LCAS / UCAS high
OE high pulse width
Data output hold time after LCAS / UCAS
low
Output disable delay from WE
WE pulse width for output disable when
LCAS / UCAS high
tPC
tCP
tRASP
tCPA
tCPRH
tOEHC
tOEP
tCOH
tWHZ
tWPZ
VG26(V)(S)18165
-5
-6
Unit
Min
Max
Min
Max
20
-
25
- ns
10
-
10
- ns
Notes
50
105
-
30
30
-
60
105 ns
22
-
35 ns 11, 15
35
- ns
5
-
5
- ns
10
-
10
- ns
5
-
5
- ns
3
10
3
10 ns
10
-
10
- ns
EDO Page Mode Read Modify Write Cycle
Parameter
Symbol
EDO page mode read- modify- write cycle
LCAS / UCAS precharge to WE delay time
EDO page mode read- modify- write cycle
time
tCPW
tPRWC
VG26(V)(S)18165
-5
-6
Unit
Min
Max
Min
Max
45
-
55
- ns
56
-
68
- ns
Notes
11
Document:1G5-0179
Rev.1
Page 10
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