VG26V18165C View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG26V18165C' PDF : 27 Pages View PDF
VIS
VG26(V)(S)18165C/VG26(V)(S)18165D
1,048,576 x 16 - Bit
CMOS Dynamic RAM
DC Characteristics; 5- Volt Verion (Ta = 0 to + 70 °C, VCC= + 5V ±10 %,VSS = 0V)
Parameter
Symbol
Test Conditions
VG26(S)18165
Unit
-5
-6
Min Max Min Max
Operating current
ICC1 RAS cycling
LCAS / UCAS cycling
tRC = min
- 160
- 145 mA
Standby current
ICC2 TTL interface
RAS,LCAS / UCAS = VIH
Dout = High-Z
2
-
2 mA
CMOS interface
RAS, CAS ≥ Vcc -0.2V
Dout = High-Z
1
-
1 mA
RAS-only
refresh current
ICC3
RAS cycling,
LCAS / UCAS = VIH
tRC = min
- 160
- 145 mA
EDO page mode
current
ICC4 tRC = min
- 90
- 80 mA
CAS-before-RAS
refresh current
ICC5 tRC = min
RAS, LCAS / UCAS cycling
- 160
- 145 mA
Self-refresh current
ICC6
tRAS ≥ 100µs
- 500
- 500 µA
Notes
1, 2
1, 2
1, 3
1, 2
Input leakage current
ILI
0V ≤ VIN ≤ VCC + 0.5V
-5
5 -5
5 µA
Output leakage current
Output high Voltage
ILO
0V ≤ VOUT ≤ VCC + 0.5V
Dout = Disable
VOH IOH = - 5mA
-5
5 -5
5 µA
2.4
- 2.4
-V
Output low voltage
VOL IOL = + 4.2mA
- 0.4
- 0.4 V
Notes:
1. ICC is specified as an average current. It depends on output loading condition and cycle rate when the
device is selected. ICC max is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL.
3. For ICC4, address can be changed once or less within one EDO page mode cycle time.
Document:1G5-0179
Rev.1
Page 6
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