VG4616321B View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG4616321B' PDF : 82 Pages View PDF
VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V ± 0.3V, Ta = 0~70°C) (Note: 6, 7, 8, 9, 10) *** CL is CAS Latency.
symbol
A.C. Parameter
-5
-6
-7
Min. Max. Min. Max. Min. Max. unit
tRC
Row cycle time
45
54
62
tRCD RAS to CAS delay
15
18
20
tRP
Precharge to refresh/row activate com- 15
18
20
ns
mand
tRRD Row activate to row activate delay
10
12
14
tRAS Row activate to precharge time
30 100,000 36 100,000 40 100,000
tWR Write recovery time
1
1
1
CLK
tCK1
CL* = 1 14
16
18
tCK2 Clock cycle time
tCK3
7
8
9
5
6
7
tCH
Clock high time
1.5
2
2.5
tCL
Clock low time
tAC1
tAC2
Access time from CLK
(positive edge)
tAC3
1.5
2
2.5
CL* = 1
ns
11
13
15
CL* = 2
5
5
6
CL* = 3
4.5
5
5.5
tT
Transition time of CLK (Rise and Fall) 0.5 10 0.5 10 0.5 10
tCCD CAS to CAS Delay time
1
1
1
CLK
tOH Data output hold time
2
2.5
2.5
tLZ
Data output low impedance
2
2
2
tHZ1
CL = 1
tHZ2 Data output high impedance CL = 2
3
5
3
5
3
6
3
5
3
5
3
6
ns
tHZ3
CL = 3
3
5
3
5
3
5
tIS
Data/Address/Control Input setup time 1
1
1.5
tIH
Data/Address/Control Input hold time
1
1
1
tSRX Minimum CKE ”High”for Self-Refresh exit 1
1
1
CLK
tPDE Power Down Exit set-up time
3
4
5
ns
tRSC (Special) Mode Register Set Cycle time 2
2
2
CLK
tBWC Block Write Cycle time
1
1
1
CLK
tDAL2
Data-in to ACT Command
(CL = 2) 1clk
+tRP
1clk+
tRP
1clk
+tRP
tDAL3
(CL = 3)
1clk
+tRP
1clk+
tRP
1clk
+tRP
tBPL Block Write to Precharge command
1
1
1
CLK
tREF Refresh time
32
32
32 ms
Document:1G5-0145
Rev.1
Page 23
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