VG4616321B View Datasheet(PDF) - Vanguard International Semiconductor
Part Name
Description
MFG CO.
'VG4616321B' PDF : 82 Pages View PDF
VIS
Preliminary
Latency relationship to frequency (Unit : clock cycles)
-5 Version (Calculation with tCK = 5ns ~ 30ns)
Clock period
tRC
(tCK)
45
tRP
tRRD
15
10
30ns
2
1
1
20ns
3
1
1
15ns
3
1
1
10ns
5
2
1
5ns
9
3
2
-6 Version (Calculation with tCK = 6ns ~ 30ns)
Clock period
tRC
tRP
(tCK)
54
18
30ns
2
1
20ns
3
1
15ns
4
2
10ns
6
2
6ns
9
3
tRRD
12
1
1
1
2
2
-7 Version (Calculation with tCK = 7ns ~ 30ns)
Clock period
tRC
tRP
(tCK)
62
20
30ns
3
1
20ns
4
1
15ns
5
2
10ns
7
2
7ns
9
3
tRRD
12
1
1
1
2
2
tRAS
30
1
2
2
3
6
tRAS
36
2
2
3
4
6
tRAS
36
2
2
3
4
6
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
tRSC
10
1
1
1
1
2
tRCD
15
1
1
1
2
3
tRSC
12
1
1
1
2
2
tRCD
18
1
1
2
2
3
tRSC
14
1
1
1
2
2
tRCD
20
1
1
2
2
3
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ (simultaneously) when all input signals are held “NOP”
state and CKE = ”H”, DQM = ”H”. The CLK signals must be started at the same time.
2) After power-up, a pause of 200u secouds minimum is required. Then, it is recommended that
DQM is held “high” (VDD levels) to ensure DQ output to be in the high impedance.
3) Both banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 8 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of
the device. Sequence of 4 and 5 may be changed.
Document:1G5-0145
Rev.1
Page 26
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