VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Figure 6.1 Clock Suspension During Burst Read (Using CKE)
(Burst Length = 4, CAS Latency = 1)
CLK
CKE
CS
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK1
RAS
CAS
WE
BS
BS
A9
A0 ~ A8
RAx
RAx CAx
DQM
DQ
Hi-Z
Ax0
Ax1
Ax2
tHZ
Ax3
Activate
Command
Bank A
Clock Suspend Clock Suspend
1 Cycle
2 Cycles
Read
Command
Bank A
Clock Suspend
3 Cycles
Note: CKE to CLK disable/enable = 1 clock
Document:1G5-0145
Rev.1
Page 32