VIS
Preliminary
Figure 14.1 Interleaving Column Read Cycle
(Burst Length = 4, CAS Latency = 1)
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
CLK
CKE
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK1
CS
RAS
CAS
WE
DSF
BS
A9
RAx
RBw
A0 ~ A8
DQM
RAx CAx
RBw CBw
CBx
CBy
CAy
CBz
tRCD tAC1
DQ
Hi-Z
Ax0 Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 By0 By1 Ay0 Ay1 Bz0 Bz1 Bz2 Bz3
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Precharge
Command
Bank B
Bank A
Precharge
Command
Bank B
Document:1G5-0145
Rev.1
Page 54