VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Figure 15.2. Interleaved Column Write Cycle (Burst Length = 4, CAS Latency = 2)
CLK
CKE
CS
RAS
CAS
WE
DSF
BS
A9
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
t
CK2
RAx
RBw
A0 ~ A8
RAx
CAx
RBw
CBw
CBx
CBy
CAy
CBz
DQM
DQ
Hi-Z
tRCD
tRRD
tRP
tWR
tRP
DAx0 DAx1 DAx2 DAx3 DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3
Activate
Command
Bank A
Write
Command
Bank A
Activate
Write
Command Command
Bank B Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank A
Precharge
Command
Bank B
Document:1G5-0145
Rev.1
Page 58