VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Figure 18.1. Full Page Read Cycle (Burst Length = Full Page, CAS Latency = 1)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
High
t
CK1
CS
RAS
CAS
WE
DSF
BS
A9
RAx
RBx
RBy
A0 ~ A8
RAx CAx RBx
CBx
RBy
DQM
tRRD
tRP
DQ Hi-Z
Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Bx+7
Activate
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Precharge
Command
Bank B
Burst Stop
Command
Activate
Command
Bank B
Document:1G5-0145
Rev.1
Page 66