VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Figure 19.2 Full Page Write Cycle (Burst Length = Full Page, CAS Latency = 2)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE High
t
CK2
CS
RAS
CAS
WE
DSF
BS
A9
RAx
RBx
RBy
A0 ~ A8
RAx
CAx
RBx
CBx
RBy
DQM
DQ
DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6
Activate
Command
Bank A
Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Data is ignored
Precharge Activate
Command Command
Bank B Bank B
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does
not terminate when the burst
length is satisfied;the burst counter
increments and continues bursting
beginning with the starting address.
Burst Stop
Command
Document:1G5-0145
Rev.1
Page 70