VV0670P001 View Datasheet(PDF) - Vision
Part Name
Description
MFG CO.
'VV0670P001' PDF : 36 Pages View PDF
Colour Processor Interface ASIC
2.2.3 DRAM Interface
In order to perform video capture and compression, CPiA depends upon an a frame store provided by a
single, low cost DRAM. The integral DRAM controller is designed to support standard 256K x 16 EDO
devices, with access times better than or equal to 60ns. Timing diagrams showing bus read and write cycles
are highlighted below. As seen in Section 2.2.2, the compression algorithm uses two main data structures
within the DRAM:
• The Framestore holds a copy of the previous image uploaded to the host. The DE uses this information
to determine significant differences between the FS image and the next image read from the VP.
• The Run Length Buffer stores the current frame in a run-length encoded form, ready for upload by the DS/
USB to the host.
RAMD[15:0]
XX
RAMLCAS_n
tCAC tOFF
tAA
XX
tRAC
DATA
VALID
tCLZ
XX
tCPA
tRCS
XX
tCAS, tCLCH
RAMUCAS_n
tCSH
tRCD
tRRH, tRCH
RAMWE_n
RAMRAS_n
tASR
tRAH
tASC
tCAH
tRAS, tRASP
tAR
tRSH
tRC
tCRP
tRP
RAMA[8:0]
row
tCHR col
col
row
col
tACH
DRAM Read Cycle Timing
RAMRAS_n
RAMUCAS_n
RAMLCAS_n
RAMA[8:0]
RAMWE_n
RAMD[15:0]
tRASP
tRWL
tRSH
tCRP
tASR
row
tCSH
tRCD
tRAH
tASC
tAR
tCAS
tCLCH
tACH
tCAH
col
tWCS
tPC
tCP
col
tCWL
tWP
tDS
tDH
DATA VALID
tWCR
DRAM Write Cycle Timing
tRP
row
V:\apps\cpia\docs\cpia datasheet\cpia_datasheet4.fm
02/07/98
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