VV0670P001 View Datasheet(PDF) - Vision
Part Name
Description
MFG CO.
'VV0670P001' PDF : 36 Pages View PDF
Colour Processor Interface ASIC
Parameter
tAA
tACH
tAR
tASC
tASR
tCAC
tCRP
tCSR
tDH
tDS
tRAC
tRAS
tRRH
tRCD
tRCS
tRP
tRWL
tWCH
tWCS
tWP
DRAM
requirement (ns)
Note 1
>30
>15
>45
>0
>0
>17
>5
>5
>10
>0
>60
>60
>0
14<tRCD<45
>0
>40
>15
>10
>0
>5
CPIA DRAM Interface Timing Parameters
CPiA DRAM Timing (ns)
Note 2
min
max
Parameter
DRAM
requirement (ns)
Note 1
43
58
52
58
68
72
17
21
68
72
19
26
68
72
28
40
28
40
28
40
63
67
68
72
68
72
28
40
28
40
68
72
52
57
28
40
17
20
52
57
tCAS
tCAH
tCHR
tCLCH
tCLZ
tCP
tCPA
tCSH
tCWL
tOFF
tPC
tRAH
tRASP
tRC
tRCH
tREF
tRPC
tT
tWCR
tRSH
>10
>10
>10
>10
0
>8
>35
>45
>10
0<tOFF<15
>25
>10
>60
>105
>0
<8ms
>5
<2
>45
>15
CPiA DRAM Timing (ns)
Note 2
min
max
28
40
28
40
28
40
28
40
0
0
28
40
62
65
68
72
52
57
5.5
6
68
72
11
21
68
72
136
144
68
72
-
16us
28
40
0.5
2
68
72
28
40
Note 1 - DRAM timing parameters extracted from DRAM manufacturer ‘s -6 worst-case spec data tables. Due to some variation in manufacturer’s figures it
is recommended required values presented in this table are closely checked against the data tables from specific target DRAM manufacturers.
Note 2 - Min and Max timing derived from worst and best case design simulation wih respect to process parameter derating with supply voltage and Tj. All
timing parameters listed have been verified and validated through device characterisation with Ta@25C, VDD=VDDA=5V.
Framestore and Run Length Buffer DRAM partitioning
Data Structure
Size (bytes) Size (Kbytes)
Framestore (FS)
Run-Length Buffer (RLB)
Total (FS + RLB)
202752
205124
407876
198
~201
~399
V:\apps\cpia\docs\cpia datasheet\cpia_datasheet4.fm
02/07/98
15
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