VV5409 View Datasheet(PDF) - Vision
Part Name
Description
MFG CO.
'VV5409' PDF : 39 Pages View PDF
VV5409 CMOS Monochrome Sensor Datasheet (Restricted) Rev 1.0
stop start
SDA
start
stop
...
SCL
tbuf
tlow tr
tf
...
thd;sta
thd;sta
thd;dat
thigh tsu;dat
tsu;sta
tsu;sto
All values referred to the minimum input level (high) = 3.5V, and maximum input level (low) = 1.5V
Figure 6.11 : Serial Interface Timing Characteristics
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VV5409 CMOS Monochrome Sensor Datasheet (Restricted) Rev 1.0
7. Clock Signal
VV5409 system clock is supplied from an external clock source, directly driving the CLKI pin. This pin has an
internal Schmitt buffer. There is no support for a crystal oscillator.
Clock
Source
CLKI
VV5409
CLOCK CLK
DIVISION
Figure 7.1 : External Clock Source
If the clock is generated for the video sensor by a host controller, it must be active during serial-interface
communications for at least 16 clock cycles, before the serial communications start bit, and at least 16 cycles
after the serial communications stop bit.
The synchronisation input, SIN, synchronises the clock divider logic in addition to the main clock generation,
and the video timing control block.
For greater flexibility the pixel frequency (for 4 wire output format) can be divided by 2, 4, 8, or 16. The pixel
clock frequency is a further factor of 2 down for 2-wire, or a factor of 4 for bit-serial mode.
The clock signal must be a square wave with a 50% (±10%) mark:space ratio. Table 7.1 specifies the
maximum pixel clock frequencies for the module. Table 7.2 specifies the relationship between the input clock,
CLKI, and the pixel clock frequency for the different settings of the sensor’s internal clock divider.
This translates into a maximum input clock frequency of 14.31818 MHz if a pixel clock divisor of 2 is used
(the default - Table 7.2).
MHz
Maximum Pixel Rate
7.15909
Table 7.1 : Maximum Pixel Clock Rate
Clock Divisor Setting
Pixel Clock Divisor
002
2
012
4
102
8
112
16
Table 7.2 : Clock Divisor Values
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