VV5409 View Datasheet(PDF) - Vision
Part Name
Description
MFG CO.
'VV5409' PDF : 39 Pages View PDF
VV5409 CMOS Monochrome Sensor Datasheet (Restricted) Rev 1.0
9. Other Features
9.1 Microphone Amplifier
The internal Microphone amplifier, comprises 3 separate amplifiers. The first 2 in the chain have
programmable gain values (x 1, x 2, x 4 and x 8). The third amplifier is configured as a voltage follower, and
drives the AOUT pin. Pin AIN is the input to the first amplifier in the chain.
The gain of each of the first two amplifiers, is independently controllable through the serial-interface register
at1. There are 7 possible overall system gains: x 1, x 2, x 4, x 8, x 16, x 32, and x 64.
The input, and output voltage ranges, should lie within the ADCtop and ADCbot voltages. The mid-point of
these two references is used as the virtual ground for the first two amplifiers.
The output amplifier, can drive a 2v peak-peak load (1.3v DC offset) with 1k ohm minimum impedance. The
compensation capacitor for the output amplifier is external. By varying the AC-coupling capacitor on the input,
and the compensation capacitor on the output, the frequency response of the amplifier can be modified.
Input, and output voltage ranges are from the voltage reference ADCbot to the ADCtop voltage reference.
The Microphone amplifier setup register, also allows the amplifiers to be powered-down, and there is an
option to multiplex internally the output of the final amplifier during the embedded “End-of-Line” sequence,
on to the input of the 8-bit ADC used to digitise pixel-data. The digitised data for 2 consecutive samples,
appears as the 2 supplementary bytes in the 6-byte end of line embedded escape sequence. Thus the video-
data stream contains 2 consecutive samples of the output of the Microphone amplifier once per line.
Bit
Function
Default
Comment
1:0 2-bit gain value for 1st gain stage, a0[1:0]
00
00: 1st Stage Gain = x 1
01: 1st Stage Gain = x 2
10: 1st Stage Gain = x 4
11: 1st Stage Gain = x 8
3:2 2-bit gain value for 2nd gain stage, a1[1:0]
00
00: 2nd Stage Gain = x 1
01: 2nd Stage Gain = x 2
10: 2nd Stage Gain = x 4
11: 2nd Stage Gain = x 8
4 Digitise Microphone Amplifier Output
Off / On
0
If this bit is selected, the ADC will
convert the output from the microphone
amplifier
5 Pad to supply analogue input to
Microphone amplifier
Off / On
1
If this bit is reset, the pad will supply a
signal holdpix which will inhibit the ADC
operating
6 Power down microphone amplifier
0
Off / On
7 Microphone Amplifier Digitisation Mode
EAV / Always
0
Digitise the Microphone output, either
only during the end of active video
embedded escape sequence, or
always
Table 9.1 : [121] - Microphone Amplifier Setup Register AT1
The register values shown in Table 9.2 correspond to actual gain values. Register: at1 on VV5409. Default
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VV5409 CMOS Monochrome Sensor Datasheet (Restricted) Rev 1.0
is 15.
Gain register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Actual gain 1 2 4 8 2 4 8 16 4 8 16 32 8 16 32 64
Table 9.2 : Audio Gain register Settings
9.2 Debounced Switch Input
VV5409 provides a special debounced digital input pin, FST/DIN, for switches. When FST/DIN is enabled as
a debounced switch input, a low on the DIN sets a set/reset latch. The value of this latch, is part of status
register status0, and thus can be observed through the serial-interface register data contained in the start-
of-field line. At the end of a start-of-field line, the latch is reset.
This input is primarily intended for a user to “mark” the required frame, by pressing a button perhaps on a
remote camera head.
This feature can be enabled by bits 6 and 7 of the fg_modes register (see Table 6.11).
9.3 Serial-Interface Programmable Pins
The FST and QCK can be re-configured to follow the values of bits 1 and 2 in the serial-interface register
pin_mapping. This is to allow remote control of a electro-mechanical system, for example two different zoom
settings, in a remote camera head through the serial-interface.
Rpullup
Switch
Inverting
Schmitt
Buffer
DIN
Set/Reset
Latch
SQ
To status
reg status0
Cfilter
R QN
Reset at end of
status line
Figure 9.1 : Debounced Switch Input
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