VV6301 View Datasheet(PDF) - Vision
Part Name
Description
MFG CO.
'VV6301' PDF : 51 Pages View PDF
CMOS Sensor; Customer Datasheet, Rev 3.0, 25 September 2000
VV5301 & VV6301
VV5301/6301
Gain binary code
Effective system gain
101
2.667
110
1.600
111
8.000
Table 24 : System Gain
The undivided input crystal clock is used by the clock generator circuitry, elements of the serial interface and a small number of
other registers in the design. The remaining digital logic and the analogue circuitry, use internally generated clocks, namely the
pixel clock and the faster ADC clocks. These clocks are all slower versions of the crystal clock. The ADC clocks may be up to half
the crystal frequency, but can be further divided by factors of 2, 4 or 8. The pixel clock is lower frequency than the ADC clock.
Bit
Function
Default
Comment
1:0 Clock divisor value
0
Pixel clock = Crystal clock ÷2n+1
Table 25 : [37],[25] - Clock Divisor Value
Bit
Function
2:0 Gain limit
Default
Comment
7
The programmed gain cannot be greater than this
value
Table 26 : [38],[26] - Gain Limit
Bit
Function
Default
Comment
7:0 Exposure lower threshold
85
Table 27 : [39],[27] - Exposure Lower Threshold
Bit
Function
Default
Comment
7:0 Exposure centre threshold
100
Table 28 : [40],[28] - Exposure Centre Threshold
Bit
Function
Default
Comment
7:0 Exposure higher threshold
115
Table 29 : [41],[29] - Exposure Higher Threshold
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