VV6301 View Datasheet(PDF) - Vision
Part Name
Description
MFG CO.
'VV6301' PDF : 51 Pages View PDF
VV5301 & VV6301
Serial Control Bus
Bit
6
7
Function
Default
Comment
unused
RST/MRST clock select
0
0
0 - adck0
1 - adck1
Table 34 : [118],[76] - Analogue Control Register 0
Bit
0
1
2
3
4
7:5
Function
Default
Comment
Enable Mag_B0
0
Double magnitude of B0 DAC current
Off/On
New PXRDB scheme
0
Off/On
B1 Offset DAC High Gain Select
0
B1_HG
low (x1)/High (x2)
Stand-by
Off/On
unused
RST/MRST phase select
0
Powers down ALL analogue circuitry
and the majority of the digital logic
0
000
The RST/MRST timing signals can be
delayed by up to 7 adck periods prior
to transfer to the analogue circuits.
000 - no delay
001 - 1 adck period delay
010 - 2 adck period delay
011 - 3 adck period delay
100 - 4 adck period delay
101 - 5 adck period delay
110 - 6 adck period delay
111 - 7 adck period delay
Table 35 : [119],[77] - Analogue Control Register1
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cd5301_6301f-3-0.fm
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