WM8731CSEFL/R View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
WM8731CSEFL/R
Cirrus Logic
'WM8731CSEFL/R' PDF : 65 Pages View PDF
WM8731 / WM8731L
MASTER CLOCK TIMING
XTI/MCLK
tXTIL
tXTIH
tXTIY
Production Data
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
XTI/MCLK System clock pulse width
high
tXTIH
XTI/MCLK System clock pulse width
tXTIL
low
XTI/MCLK System clock cycle time
tXTIY
XTI/MCLK Duty cycle
TEST CONDITIONS
MIN
18
18
54
40:60
TYP
MAX
60:40
UNIT
ns
ns
ns
XTI/MCLK
tCOP
CLKOUT
CLKOUT
(DIV X2)
Figure 2 Clock Out Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
CLKOUT propagation delay from
tCOP
XTI/MCLK falling edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
10
ns
w
PD, Rev 4.9, October 2012
15
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