WM8731 / WM8731L
DIGITAL AUDIO INTERFACE – MASTER MODE
Production Data
BCLK
ADCLRC
WM8731
CODEC
DACLRC
ADCDAT
DACDAT
Note: ADC and DAC can run at different rates
Figure 3 Master Mode Connection
DSP
ENCODER/
DECODER
BCLK
(Output)
ADCLRC
DAC/LRC
(Outputs)
ADCDAT
t
DL
t DDA
DACDAT
t DST
t DHT
Figure 4 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, HPVDD, DBDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
ADCLRC/DACLRC
tDL
propagation delay from
BCLK falling edge
ADCDAT propagation delay
tDDA
from BCLK falling edge
DACDAT setup time to
tDST
BCLCK rising edge
DACDAT hold time from
tDHT
BCLK rising edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
10
ns
0
35
ns
10
ns
10
ns
w
PD, Rev 4.9, October 2012
16