WM8742 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8742' PDF : 65 Pages View PDF
WM8742
MASTER CLOCK TIMING
Production Data
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC
PARAMETER
Master Clock Timing Information
MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
MCLK Duty cycle
Table 1 MCLK Timing Requirements
SYMBOL
tMCLKH
tMCLKL
tMCLKY
TEST CONDITIONS
PCM DIGITAL AUDIO INTERFACE TIMINGS
MIN
10
10
27
40:60
TYP
MAX
UNIT
ns
ns
ns
60:40
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK
rising edge
tBCY
tBCH
tBCL
tLRSU
LRCLK hold time from
tLRH
BCLK rising edge
DIN set-up time to BCLK
tDS
rising edge
DIN hold time from BCLK
tDH
rising edge
Table 2 Digital Audio Interface Timing Requirements
MIN
TYP
MAX
40
16
16
8
8
8
8
UNIT
ns
ns
ns
ns
ns
ns
ns
w
PD, Rev 4.3, February 2013
12
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