WM8742 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8742' PDF : 65 Pages View PDF
Production Data
WM8742
REGISTER
ADDRESS
R0
DACLLSB
Attenuation
00h
BITS
[4:0]
5
LABEL
LAT[4:0]
UPDATE
R1
[4:0]
DACLMSB
Attenuation
01h
5
LAT[9:5]
UPDATE
R2
[4:0]
DACRLSB
Attenuation
5
02h
RAT[4:0]
UPDATE
R3
[4:0]
DACRMSB
Attenuation
5
03h
RAT[9:5]
UPDATE
Table 24 Attenuation Control
DEFAULT
00 (0dB)
0
00 (0dB)
0
00 (0dB)
0
00 (0dB)
0
DESCRIPTION
LSBs of attenuation data for left channel in 0.125dB steps. See
Table 25 for details.
Attenuation data load control for left channel.
0 = Store LAT[4:0] value but don’t update
1 = Store LAT[4:0] and update attenuation on registers 0-3
MSBs of attenuation data for left channel in 4dB steps. See Table
25 for details.
Attenuation data load control for left channel.
0 = Store LAT[9:5] value but don’t update
1 = Store LAT[9:5] and update attenuation on registers 0-3
LSBs of attenuation data for right channel in 0.125dB steps. See
Table 25 for details.
Attenuation data load control for right channel.
0 = Store RAT[4:0] value but don’t update
1 = Store RAT[4:0] and update attenuation on registers 0-3
MSBs of attenuation data for right channel in 4dB step. See Table
25 for details.
Attenuation data load control for right channel.
0 = Store RAT[9:5] value but don’t update
1 = Store RAT[9:5] and update attenuation on registers 0-3
Note:
1. The UPDATE bit is not latched. If UPDATE=0, the attenuation value will be written to the pre-latch but not applied to
the relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next
input sample.
DAC OUTPUT ATTENUATION
Registers LAT[9:0] and RAT[9:0] control the left and right channel attenuation. Table 25 shows how
the attenuation levels are configured by the 10-bit words.
L/RAT[9:0]
ATTENUATION LEVEL
000(hex)
0dB
001(hex)
-0.125dB
:
:
:
:
:
:
3FE(hex)
-127.75dB
3FF(hex)
-dB (mute)
Table 25 Attenuation Control Levels
ATTENUATION CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and
right channel DACs from the next audio input sample. No update to the attenuation registers is
required for ATC to take effect. Right channels register settings are preserved regardless of the
status of ATC.
REGISTER ADDRESS BIT LABEL
R4
2
ATC
Volume Control
04h
Table 26 Attenuator Control Mode
DEFAULT
0
DESCRIPTION
Attenuator Control Mode:
0 = Right channels use Right
attenuation
1 = Right Channels use Left
Attenuation
w
PD, Rev 4.3, February 2013
31
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