WM8742 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8742' PDF : 65 Pages View PDF
WM8742
Production Data
ZERO FLAG OUTPUT
The WM8742 has one zero flag output pin, ZFLAG (pin 21). The zero flag feature is only valid for
PCM data.
The WM8742 asserts Logic 1 on the ZFLAG pin when a sequence of more than 1024 zeros is input to
the chip. The default value is a logical AND of both left and right channels. Under software control,
the user can also set the zero flag pin to respond to either the left channel OR the right channel.
The zero flag pin can be used to control external muting circuits if required.
REGISTER
ADDRESS
R4
Volume Control
04h
BIT LABEL DEFAULT
6:5 ZEROFLR
00
[1:0]
Table 32 Zero Flag Output
DESCRIPTION
Zero flag output:
00 = Pin assigned to logical AND of
LEFT and RIGHT channels
01 = Pin assigned to LEFT channel
10 = Pin assigned to RIGHT
channel
11 = ZFLAG disabled
ZFLAG FORCE HIGH CONTROL
It is possible to force the ZFLAG pin to Logic 1 by setting ZFLAG_HI=1 in R7. This is useful in
situations where an application processor may require manual control of an external mute circuit.
Setting ZFLAG_HI=0 will allow the ZFLAG pin to function as defined by ZFLAGLR[1:0].
REGISTER ADDRESS BIT LABEL
R6
7 ZFLAG_HI
Mode Control 1
06h
Table 33 ZFLAG Force High Control
DEFAULT
0
DESCRIPTION
ZFLAG Force High Control
0 = Normal operation
1 = Output Logic 1
INFINITE ZERO DETECT
The IZD register configures the operation of the WM8742 analogue mute in conjunction with the zero
flag feature. Table 20 shows the interdependency of the MUTEB pin, the IZD register and the zero
flag.
REGISTER ADDRESS BIT
R4
4
Volume Control
04h
LABEL
IZD
Table 20 Infinite Zero Detect Control
DEFAULT
0
DESCRIPTION
IZD control of analogue mute:
0 = Never analogue mute
1 = Analogue mute when ZFLAG
set
w
PD, Rev 4.3, February 2013
34
Share Link: 
