WM8742 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8742' PDF : 65 Pages View PDF
Production Data
WM8742
REGISTER
ADDRESS
R0
DACLLSB
Attenuation
00h
BITS
[4:0]
5
NAME
LAT[4:0]
UPDATE
DEFAULT
00 (0dB)
0
Table 53 R0 DACL LSB Attenuation Control Register
DESCRIPTION
LSBs of attenuation data for left channel in 0.125dB steps. See Table
25 for details.
Attenuation data load control for left channel.
0 = Store LAT[4:0] value but don’t update
1 = Store LAT[4:0] and update attenuation on registers 0-3
REGISTER
ADDRESS
R1
DACLMSB
Attenuation
01h
BITS
[4:0]
5
NAME
LAT[9:5]
UPDATE
DEFAULT
00 (0dB)
0
Table 54 R1 DACL MSB Attenuation Control Register
DESCRIPTION
MSBs of attenuation data for left channel in 4dB steps. See Table 25
for details.
Attenuation data load control for left channel.
0 = Store LAT[9:5] value but don’t update
1 = Store LAT[9:5] and update attenuation on registers 0-3
REGISTER
ADDRESS
R2
DACRLSB
Attenuation
02h
BITS
[4:0]
5
NAME
RAT[4:0]
UPDATE
DEFAULT
00 (0dB)
0
Table 55 R2 DACR LSB Attenuation Control Register
DESCRIPTION
LSBs of attenuation data for right channel in 0.125dB steps. See
Table 25 for details.
Attenuation data load control for right channel.
0 = Store RAT[4:0] value but don’t update
1 = Store RAT[4:0] and update attenuation on registers 0-3
REGISTER
ADDRESS
R3
DACRMSB
Attenuation
03h
BITS
[4:0]
5
NAME
RAT[9:5]
UPDATE
DEFAULT
00 (0dB)
0
Table 56 R3 DACR MSB Attenuation Control Register
DESCRIPTION
MSBs of attenuation data for right channel in 4dB step. See Table 25
for details.
Attenuation data load control for right channel.
0 = Store RAT[9:5] value but don’t update
1 = Store RAT[9:5] and update attenuation on registers 0-3
w
PD, Rev 4.3, February 2013
45
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