WM8768 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8768' PDF : 38 Pages View PDF
WM8768
BCLK
tBCH
tBCL
tBCY
LRCLK
DIN1/2/3/4
tDS
tLRH
Figure 5 Digital Audio Data Timing – Slave Mode
tLRSU
Production Data
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise
stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
BCLK cycle time
tBCY
BCLK pulse width high
tBCH
BCLK pulse width low
tBCL
LRCLK set-up time to BCLK
rising edge
tLRSU
LRCLK hold time from
tLRH
BCLK rising edge
DIN1/2/3/4 set-up time to
tDS
BCLK rising edge
DIN1/2/3/4 hold time from
tDH
BCLK rising edge
Table 3 Digital Audio Data Timing – Slave Mode
TEST CONDITIONS
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
w
PD Rev 4.3 July 2010
10
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