WM8768 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8768' PDF : 38 Pages View PDF
Production Data
WM8768
BCLK
(Output)
tDL
LRCLK
(Output)
DIN1/2/3/4
tDST
Figure 3 Digital Audio Data Timing – Master Mode
tDHT
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
LRCLK propagation delay
tDL
from BCLK falling edge
DIN1/2/3/4 setup time to
tDST
BCLK rising edge
DIN1/2/3/4 hold time from
tDHT
BCLK rising edge
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0
10
ns
10
ns
10
ns
Table 2 Digital Audio Data Timing – Master Mode
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
WM8768
DAC
LRCLK
DIN1/2/3/4
4
DSP/
DECODER
Figure 4 Audio Interface – Slave Mode
w
PD Rev 4.3 July 2010
9
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