WM8768 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8768' PDF : 38 Pages View PDF
WM8768
Production Data
By default, LRCLK and DIN1/2/3/4 are sampled on the rising edge of BCLK and should ideally
change on the falling edge. Data sources that change LRCLK and DIN1/2/3/4 on the rising edge of
BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK
to the inverse of that shown in Figure 13, Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18.
REGISTER ADDRESS BIT
0000011
3
Interface Control
LABEL
BCP
DEFAULT
0
DESCRIPTION
BCLK Polarity
0 : normal BCLK polarity
1: inverted BCLK polarity
The IWL[1:0] bits are used to control the input word length.
REGISTER ADDRESS BIT LABEL DEFAULT
DESCRIPTION
0000011
Interface Control
5:4
IWL
[1:0]
00
Input Word Length
00 : 16 bit data
01: 20 bit data
10: 24 bit data
11: 32 bit data
Note: If 32-bit mode is selected in right justified mode, the WM8768 defaults to 24 bits.
In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the
DAC is programmed to receive 16 or 20 bit data, the WM8768 pads the unused LSBs with zeros. If
the DAC is programmed into 32 bit mode, the 8 LSBs are ignored.
Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that LRCLK is high for a
minimum of 24 BCLKs and low for a minimum of 24 BCLKs. If exactly 32 bit clocks occur in one
left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode.
A number of options are available to control how data from the Digital Audio Interface is applied to
the DAC channels.
DAC OUTPUT PHASE
The DAC phase control word determines whether the output of each DAC is non-inverted or inverted
REGISTER ADDRESS BIT
0000011
8:6
DAC Phase
LABEL
PHASE
[2:0]
DEFAULT
000
Bit
0
1
2
DESCRIPTION
DAC
Phase
DAC1L/R 1 = invert
DAC2L/R 1 = invert
DAC3L/R 1 = invert
0001111
DAC4 Control
3 PHASE4
0
N/A
DAC4L/R 1 = invert
DIGITAL ZERO CROSS-DETECT
The digital volume control also incorporates a zero cross detect circuit which detects a transition
through the zero point before updating the digital volume control with the new volume. This is
enabled by control bit DZCEN.
REGISTER ADDRESS BIT LABEL
0001001
0 DZCEN
DAC Control
DEFAULT
0
DESCRIPTION
DAC Digital Volume Zero Cross
Enable:
0: Zero cross detect enabled
1: Zero cross detect disabled
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PD Rev 4.3 July 2010
22
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