WM8768 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8768' PDF : 38 Pages View PDF
WM8768
Production Data
MASTER MODE SELECT
Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRCLK
and BCLK are outputs and are generated by the WM8768. In Slave mode LRCLK and BCLK are
inputs to WM8768.
REGISTER ADDRESS BIT
0001010
5
Interface Control
LABEL
MS
DEFAULT
0
DESCRIPTION
Audio Interface Master/Slave Mode
select:
0: Slave Mode
1: Master Mode
MASTER MODE LRCLK FREQUENCY SELECT
In Master mode the WM8768 generates LRC and BCLK. These clocks are derived from the master
clock and the ratio of MCLK to LRCK is set by RATE.
REGISTER ADDRESS
0001010
Interface Control
BIT LABEL
8:6 RATE[2:0]
DEFAULT
010
DESCRIPTION
Master Mode MCLK: LRCLK ratio
select:
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
101: 768fs
MUTE PIN DECODE
The MUTE pin can either be used as an output or an input. When used as an input the MUTE pins
action can be controlled by setting the DZFM and DZFM4 bit to select the corresponding DAC for
applying the MUTE to. As an output its meaning is selected by the DZFM and DZFM4 control bits. By
default selecting the MUTE pin to represent if DAC1 has received more than 1024 midrail samples
will cause the MUTE pin to assert a softmute on DAC1. Disabling the decode block will cause any
logical high on the MUTE pin to apply a softmute to all DAC’s. For compatibility with the WM8772
register the MUTE pin decode bit is also found in the ADC control register, which is redundant on this
chip. The OR of these two register bit is taken internally.
REGISTER ADDRESS BIT
0001100
6
ADC Control
0001111
5
DAC4 control
LABEL
MPD
MPD
DEFAULT
0
0
DESCRIPTION
MUTE pin decode disable:
0: MUTE pin decode enable
1: MUTE pin decode disable
MUTE pin decode disable:
0: MUTE pin decode enable
1: MUTE pin decode disable
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PD Rev 4.3 July 2010
30
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