WM8768GEDS/RV View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8768GEDS/RV' PDF : 38 Pages View PDF
WM8768
Production Data
SAMPLING RATE
(LRCLK)
128fs
192fs
SYSTEM CLOCK FREQUENCY (MHZ)
256fs
384fs
512fs
768fs
1152fs
32kHz
4.096
6.144
8.192
44.1kHz
5.6448
8.467
11.2896
48kHz
6.144
9.216
12.288
96kHz
12.288
18.432
24.576
192kHz
24.576
36.864
Unavailable
Table 6 System Clock Frequencies Versus Sampling Rate
12.288
16.9340
18.432
36.864
Unavailable
16.384
22.5792
24.576
Unavailable
Unavailable
24.576
33.8688
36.864
Unavailable
Unavailable
36.864
Unavailable
Unavailable
Unavailable
Unavailable
HARDWARE CONTROL MODES
When the MODE pin is held high, the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, the MUTE pin controls the selection of MUTE directly, and
can be used to enable and disable the automute function. This pin becomes an output when left
floating and indicates infinite zero detect (IZD) has been detected.
DESCRIPTION
0
1
Floating
Normal Operation
Mute DAC channels
Enable IZD, MUTE pin becomes an output to indicate when IZD occurs.
L=IZD not detected, H=IZD detected.
Table 7 Mute and Automute Control
Figure 9 shows the application and release of MUTE whilst a full amplitude sinusoid is being played
at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to
decay exponentially from the DC level of the last input sample. The output will decay towards VMID
with a time constant of approximately 64 input samples. When MUTE is de-asserted, the output will
restart almost immediately from the current input sample.
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.001
0.002
0.003
Time(s)
Figure 9 Application and Release of Soft Mute
0.004
0.005
0.006
w
PD Rev 4.3 July 2010
14
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