WM8768GEDS/RV View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8768GEDS/RV' PDF : 38 Pages View PDF
WM8768
Production Data
RIGHT JUSTIFIED MODE
In right justified mode, the LSB of DIN1/2/3/4 is sampled by the WM8768 on the rising edge of BCLK
preceding a LRCLK transition. LRCLK are high during the left samples and low during the right
samples (Figure 14).
LRCIN
BCKIN
LEFT CHANNEL
1/fs
RIGHT CHANNEL
DIN1/2/3/4
123
MSB
n-2 n-1 n
LSB
123
MSB
n-2 n-1 n
LSB
Figure 14 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB of DIN1/2/3/4 is sampled by the WM8768 on the second rising edge of BCLK
following a LRCLK transition. LRCLK are low during the left samples and high during the right
samples.
1/fs
LRCIN
LEFT CHANNEL
RIGHT CHANNEL
BCKIN
DIN1/2/3/4
1 BCKIN
123
MSB
n-2 n-1 n
LSB
Figure 15 I2S Mode Timing Diagram
1 BCKIN
123
MSB
n-2 n-1 n
LSB
DSP MODE A
In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8768 on the second
rising edge on BCLK following a LRCLK rising edge. DAC channel 1 right and DAC channels 2/3/4
data follow DAC channel 1 left data (Figure 16).
LRCIN
BCKIN
DIN1
1 BCKIN
1/fs
CHANNEL 1
LEFT
CHANNEL 1
RIGHT
CHANNEL 2
LEFT
12
MSB
n-1 n 1 2
LSB
n-1 n 1 2
Input Word Length (IWL)
Figure 16 DSP Mode A Timing Diagram – DAC data input
1 BCKIN
CHANNEL 4
RIGHT
n-1 n
NO VALID DATA
w
PD Rev 4.3 July 2010
18
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