WM8772 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8772' PDF : 73 Pages View PDF
WM8772EDS – 28 LEAD SSOP
Production Data
DSP MODE A
In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8772EDS on the second
rising edge on BCLK following a LRC rising edge. DAC channel 1 right and DAC channels 2 and 3
data follow DAC channel 1 left data (Figure 26).
Figure 26 DSP Mode Audio Interface - Mode A Slave, DAC
1 BCLK
1/fs
DACLRC
1 BCLK
DACBCLK
DIN1
CHANNEL 1
LEFT
CHANNEL 1
RIGHT
CHANNEL 2
LEFT
12
MSB
n-1 n 1 2
LSB
n-1 n 1 2
Input Word Length (IWL)
CHANNEL 3
RIGHT
NO VALID DATA
n-1 n
Figure 27 DSP Mode Audio Interface - Mode A Master, DAC
The MSB of the left channel ADC data is output on DOUT and changes on the first falling edge of
BCLK following a low to high LRC transition and may be sampled on the rising edge of BCLK. The
right channel ADC data is contiguous with the left channel data (Figure 26)
Figure 28 DSP Mode Audio Interface - Mode A Slave, ADC
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PD Rev 4.2 October 2005
26
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