WM8772SEDS/RV View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8772SEDS/RV' PDF : 73 Pages View PDF
Production Data
WM8772EDS – 28 LEAD SSOP
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In
both Master and Slave modes DIN1/2/3 are always inputs to the WM8772EDS and DOUT is always
an output. The default is Slave mode.
In Slave mode, LRC and BCLK are inputs to the WM8772EDS (Figure 21). DIN1/2/3 and LRC are
sampled by the WM8772EDS on the rising edge of BCLK. ADC data is output on DOUT and
changes on the falling edge of BCLK.
By setting the control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 and LRC are
sampled on the falling edge of BCLK and DOUT changes on the rising edge of BCLK.
WM8772
CODEC
LRC
BCLK
DOUT
DIN1/2/3
DSP
ENCODER/
DECODER
3
Figure 21 Slave Mode
In Master mode, LRC and BCLK are outputs from the WM8772EDS (Figure 22). LRC and BCLK are
generated by the WM8772EDS. DIN1/2/3 are sampled by the WM8772EDS on the rising edge of
BCLK so the controller must output DAC data that changes on the falling edge of BCLK. ADC data is
output on DOUT and changes on the falling edge of BCLK.
By setting control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3 are sampled on the
falling edge of BCLK, and DOUT changes on the rising edge of BCLK.
BCLK
WM8772 LRC
CODEC DOUT
DIN1/2/3
3
DSP/
ENCODER/
DECODER
Figure 22 Master Mode
w
PD Rev 4.2 October 2005
23
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