WM8782A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8782A' PDF : 20 Pages View PDF
WM8782A
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Production Data
Figure 1 System Clock Timing Requirements
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, Slave Mode, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK duty cycle
SYMBOL
TMCLKL
TMCLKH
TMCLKY
TMCLKDS
MIN
11
11
28
40:60
TYP
MAX
60:40
Table 1 Master Clock Timing Requirements
UNIT
ns
ns
ns
w
PD, April 2010, Rev 4.8
8
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