WM8804 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

WM8804

1:1 Digital Interface Transceiver with PLL

Cirrus Logic 

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Production Data

WM8804

Note 1: S/PDIF data frames contain a maximum of 24-bits of audio data.

Note 2:

In 24 bit I2S mode, any data width of 24 bits or less is supported provided that LRCLK is high

for a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles (48 BCLK

cycles). If exactly 32 BCLK cycles occur in one LRCLK (16 high, 16 low) the chip will auto

detect and operate in 16 bit data word length mode.

Note 3: 24 bit Right Justified ‘With Flags’ Mode is not supported.

Note 4: Must be set to the same value as AIFTX_BCP.

Note 5: Must be set to the same value as AIFTX_LRP.

Note 6: MAXWL and RXWL[2:0] bits in recovered channel status data are used to truncate digital

audio interface transmitted data. The truncation replaces the lower data bits with 0. Refer to

received channel status bit description.

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PD Rev 4.1 September 2007

51

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