WM8804GEDS/R View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8804GEDS/R' PDF : 66 Pages View PDF
Production Data
WM8804
3-WIRE SERIAL CONTROL MODE REGISTER READ-BACK
Not all registers can be read. Only the device ID (registers R0, R1 and R2) and the status registers
can be read. These status registers are labelled as “read only” in the Register Map section.
The read-only status registers can be read back via the SDOUT pin. The registers can be read by
one of two methods, selected by the CONT register bit and the ‘W’ control bit. The oscillator must be
powered up before 3-wire control interface read-back is possible.
When CONT =1 and ‘W’=0, a single read-only register can be read back by writing to any other
register or to a dummy register. The register to be read is determined by the READMUX[2:0] bits.
When a write to the device is performed, the device will respond by returning the status byte in the
register selected by the READMUX register bits. This 3-wire interface read back method using a write
access is shown in Figure 9.
REGISTER ADDRESS BIT
LABEL
R29
2:0 READMUX
SPDRX1
[2:0]
1Dh
3
CONT
Table 10 Read-Back Control Register
DEFAULT
000
0
DESCRIPTION
Status Register Select
Determines which status register
is to be read back:
000 = Interrupt Status Register
001 = Channel Status Register 1
010 = Channel Status Register 2
011 = Channel Status Register 3
100 = Channel Status Register 4
101 = Channel Status Register 5
110 = S/PDIF Status Register
Continuous Read Enable
0 = Continuous read-back mode
disabled
1 = Continuous read-back mode
enabled
The SDOUT pin is tri-state unless CSB is held low; therefore CSB must be held low for the duration
of the read.
Figure 9 3-Wire Control Interface Read-Back Method 1
The second method of reading the read only status registers is If CONT=0 and ‘W’=1. Using this
method the user can read back directly from a register by reading the register address. The device
will respond with the contents of the register. The protocol for this read-back method is shown in
Figure 10.
w
PD Rev 4.1 September 2007
15
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